Co Modeling and Co Synthesis of Safety Critical Multi threaded Embedded Software for Multi Core Embedded Platforms
Jean-Pierre Talpin · 2017
Abstract : This is the final report on the findings of the USAF/OSR grant to support collaboration between INRIA (FR), University of Kaiserslautern (DE) andVirginia Tech (VA, USA) on research entitled 'Co-Modeling of Safety-Critical Multi-threaded Embedded Software for Multi-Core EmbeddedPlatforms. In this project, we consider and integrate two different model-based design flows that are based on synchronous languages: Thefirst design flow starts with a polychronous model that is in some sense a process network whose nodes are triggered whenever input valuesare available. To ensure that such systems are deterministic and can run with bounded memory, clock consistency constraints have to bechecked that are defined for the input and output streams of each node. Even if this has been successfully solved in the past individually forpure synchronous programs, and pure polychronous programs, one has to additionally determine a clock consistent schedule for the finalcode generation. In this proposal, we will develop new methods to ensure clock consistency in that we will reduce the problem to theconstructiveness of (poly)synchronous programs. This will not only lead to new procedures to check clock consistency, but due to theconstructive reasoning, we also derive schedules for code generation, and we can implement simulators for polychronous models.