An improved congestion free modified fat tree Network — On — Chip Topology
Abhijit Biswas, Md. Anwar Hussain, Alakesh Kalita · 2016
As the current decade is witnessing a shift from traditional System - On - Chip (SoC) to Network - On - Chip, but the inherent problems such as congestion, latency and delay still remains the major issues of concern. The effect of these issues in a chip may somehow be minimized by carefully designing a topology and a suitable routing algorithm which offers both path diversity and scalability. In this paper, an attempt is being made to minimize, the congestion in the internal routers of the MIN Fat Tree, by adding an extra link in each router for the purpose of interconnection amongst the router. The simulation of the resultant topology shows promising results in terms of average delay and average hop count when compared to MIN Fat Tree.