Reconfigurable Multi-Processor Network-on-Chip on FPGA
Akash S. Kumar, I Ovadia, Jos Huisken, Henk Corporaal, van Jl Jef Meerbergen, Yajun Ha · TU/e Research Portal · 2006
Abstract—Dealing with real-time constraints is always a problem in a typical System-on-chip design. It is worsened in a multi-processor system connected via a network. FPGA prototyping is a quick way to do a real-time simulation of the system and identify the potential problems. In this paper we propose a reconfigurable MPNoC architecture in which both the network and the processing nodes are configured. The flow allows for each component to be tested separately prior to testing the entire design. This allows for quick design iterations of the system. An example design of such an architecture that has been mapped onto an FPGA is presented. O I.