FAReP: Fragmentation-Aware Replacement Policy for Task Reuse on Reconfigurable FPGAs
Godwin Enemali, Adewale Adetomi, Tughrul Arslan · 2017
The use of reconfigurable chips such as FPGAs in embedded systems for many runtime applications is limited by large reconfiguration time. Techniques to circumvent this limitation relies on hardware task reuse which preserve certain circuits on the chip. However, the frequent addition and removal of circuits while preserving others on the chip will inevitably lead to fragmentation of its area, in an ongoing manner. In this paper, we present a fragmentation-aware replacement policy (FAReP) for reusing tasks on reconfigurable chips. FAReP aims not only at circumventing reconfiguration time, but also offering some defragmentation of the chip area at no extra reconfiguration cost. Our results show that FAReP leads to a reduced task rejection ratio, at least a 13% reduction in average unused chip area and up to 29% of reconfiguration time could be avoided compared to state of the art techniques based on task reuse.