Adaptive Decision Feedback Equalization With Continuous-time Infinite Impulse Response Filters
Shayan Shahramian · TSpace (University of Toronto) · 2016
In high-speed (10+Gb/s) chip-to-chip links, the primary impairments to signal integrity are noise, crosstalk, and a smooth tail in the pulse response resulting in inter-symbol interference (ISI) sometimes spanning more than 10 unit intervals (UIs). Although often simple in their implementation, continuous time linear equalizers amplify high-frequency noise and crosstalk and consume extra power. A conventional discrete-time (DT) decision feedback equalizer (DFE) is well-suited and power efficient for channels with a few dominant post-cursor ISI terms, however, the power can become prohibitive for channels with many post-cursor ISI terms. Infinite impulse response (IIR) DFEs can equalize post-cursor ISI persisting 10 or more UIs while consuming low-power comparable to just one DT tap. DFE architectures with varying numbers of DT and IIR taps are compared for use in typical wireline channels, and it is found that 2 IIR taps can offer an excellent compromise between power consumption and performance. However, an IIR DFEâ s performance degrades significantly as the feedback loop delay increases. Fortunately, adding a single DT tap can eliminate the degradation. The first ever hybrid DFE combining 1 DT and multiple (2) IIR taps is presented equalizing 24dB loss at half the bitrate while consuming 4.1mW at 10Gb/s. A novel edge based adaptation algorithm is also presented for DT DFEs which converges faster than previous algorithms while using the same high-speed circuitry and signals required for clock recovery. The edge based algorithm is extended to work for a 1 DT + 1 IIR DFE. The 1 DT + 1 IIR DFE along with integrated clock recovery and adaptation is demonstrated in 28nm FD-SOI CMOS. At 16Gb/s with a 30dB-loss channel, a BER below 10â 12 is measured over a 0.3UI timing window. The novel edge-based algorithm adapts both IIR and discrete-tap equalizer coefficients using the same high-speed circuitry and signals required for clock recovery. The adaptive DFE converges within 5us and is robust in the presence of poorly-conditioned data.