A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption
Luis Rodríguez-Flores, Miguel Morales‐Sandoval, René Cumplido, Claudia Feregrino-Uribe, Ignacio Algredo‐Badillo · 2017
Exponentiation in multiplicative groups is the most time-consuming and critical operation for implementing asymmetric cryptography for key exchange, digital signatures, and digital envelopes in security protocols. Most of the designs previously reported to support this operation are mainly devoted to achieve the highest performance. However, in current computing paradigms highly dominated by interconnected small, computing-constrained devices, small but efficient cryptographic hardware designs are better preferred. This paper presents a novel co-processor for exponentiation, having as main design goal to have a compact design well suited for constrained computing environments. As key aspect, the proposed coprocessor uses a microprogramming approach together with a pipelined datapath that processes operands digit-by-digit. The coprocessor is designed to exploit the available resources in modern FPGAs, thus reducing the usage of standard logic. The experimental results reveal that our design achieves better efficiency than other implementation approaches.