Hardware architecture for Kohonen network
Hidetoshi Onodera, Kiyoshi Takeshita, Keikichi Tamaru · 2002
A fully digital architecture for Kohonen networks suitable for VLSI implementation is proposed. The architecture has a structure similar to a content addressable memory (CAM). One work of CAM is regarded as a processing element, and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus, the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, it is estimated that a network with 96 neurons for speech recognition could be integrated on three chips and that it would operate 50 times faster than sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is compatible with current VLSI technology.>