High Level Debugging Techniques for Modern Verification Flows
Zissis Poulos · TSpace (University of Toronto) · 2014
Early closure to functional correctness of the final chip has become a crucial success factor in the semiconductor industry. In this context, the tedious task of functional debugging poses a significant bottleneck in modern electronic design processes, where new problems related to debugging are constantly introduced and predominantly performed manually. This dissertation proposes methodologies that address two emerging debugging problems in modern design flows. First, it proposes a novel and automated triage framework for Register-Transfer-Level (RTL) debugging. The proposed framework employs clustering techniques to automate the grouping of a plethora of failures that occur during regression verification. Experiments demonstrate accuracy improvements of up to 40% compared to existing triage methodologies. Next, it introduces new techniques for Field Programmable Gate Array (FPGA) debugging that leverage reconfigurability to allow debugging to operate without iterative executions of computationally-intensive design re-synthesis tools. Experiments demonstrate productivity improvements of up to 30 x vs. conventional approaches.