An Efficient High-Performance Vedic Multiplier: Review
Ravindra Suryavanshi, Sweta Khare · INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING AND MANAGEMENT · 2017
Multipliers are the most essential block of any processor.Multiplication is one of the important operations in digital signal processors.The processing speed of a ALU is depends on its logic algorithm and complexity of hardware circuitry delay.Basically delay is depending on number of bits increases.For efficient processors, delay should minimum; to minimize delay optimized hardware architecture for process is required.Vedic Multipliers are able to deal with the above credential of minimum hardware architecture.In this review a comprehensive analysis of binary multiplication algorithm and Vedic multiplication algorithm has presented.