Full Transceiver Circuit Simulation using VHDL-AMS
Jean Oudinot, S. Scotti, Jean Ravatin, Audrey Le-clercq, Jacky Lebrun · European Simulation Multiconference on Modelling and Simulation · 2002
This paper describes the successful simulation of a complete transceiver circuit with the new VHDL-AMS standard. The aim was to verify the functionality and connectivity of a complete RF transceiver chip under actual application conditions. The transceiver circuit is dedicated to E-GSM/GPRS standards for mobile phone applications. At such a level of complexity, traditional tools do not allow simulation of the design at transistor level. In addition to digital models, mixed-signal behavioural models of the transmitter, receiver and frequency synthesiser have been developed for a high level of abstraction, as required in a top-down methodology. The complete simulation of the chip took 23 minutes of CPU time for 6ms of circuit operation. For the first time we were able to verify and debug such a circuit at the top-level.