Design of residue generators with CLA/compressor trees and multi-bit EAC
Piotr Patronik, S.J. Piestrak · 2017
We propose a new approach to designing residue generators for an arbitrary moduli. Its novelty is that the carry-out bit is fed as multi-bit word back to the adder tree, while using reduction algorithms similar to the concepts of the compressor trees. For any modulus, reduction of multiple operands can be done using a carry-save adder (CSA) tree down to two vectors, which are then handled by an arbitrary 2-operand modular adder. The compressor trees built using full-adders and 5:3 compressors are analyzed. The number of reduction stages is similar to the positional CSA tree (without any carry-out values fed back) followed by the reduction circuit. The RNS applications of the proposed circuits include forward- and reverse converters as well as constant- and variable multipliers.