A 80/20 MHz 160 mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications
Chi-Weon Yoon, R. Woo, Jeonghoon Kook, Se-Joong Lee, Langmin Lee, Young-Don Bae, In-Cheol Park, Hoi-Jun Yoo · 2002
An 84 mm/sup 2/ 160 mW programmable processor in 0.18 /spl mu/m EMC technology consists of 32 b RISC with MAC, 20 MHz motion compensation accelerator for MPEG-4 at SP, 3D rendering engine with 2.2 M polygon/s at 20 MHz, and 7.125 Mb embedded DRAM with single bitline writing scheme.