Multiplier less high speed VLSI architecture for lifting based 1-D discrete wavelet transform
Vidyanand Dahiya, Manish Singhal, Amit M. Joshi · 2016
An efficient VLSI architecture of 1-D DWT based on lifting scheme is proposed for high speed applications. Multipliers are difficult to fabricate on chip and occupy more area. The paper presents multiplier-less DWT architecture. Since the lifting scheme suffers the longer critical path, irregular datapath, data dependencies. The critical path of proposed architecture is Ta which is the minimum possible critical path delay of DWT architecture. We have also used parallel flipping technique where addition and multiplication are processed in parallel manner. The proposed architecture archives 100% hardware utilization efficiency. The architecture is synthesized on Virtex-IV Xc4vfx20-12ff672 using VHDL.