Benchmarking 3D transistors for digital beamforming applications
Daniel Thompson, Mark B. Yeary, Bo Marr, Ken Prager · 2017
As sampling rates, instantaneous bandwidths, and number of channels increase, so does the amount of data to process in a digital beamformer. This processing performance is limited by two critical bottlenecks. The first bottleneck is the physical aspect of the hardware; how fast and how many cores? These properties vary across processing nodes depending on transistor density and power profile. The second bottleneck is the I/O speed and efficiency. All the data to be processed at any instance in time may not reside in the memory space of a single device and thus, requires data transfers between processors. In general, these bottlenecks limit the processing efficiency of a digital beamformer and the exact boundaries vary according to processing architecture. In this paper, we use a comparable processing node and similar software approach to benchmark the throughput and efficiency of the industry's latest CPU, GPU, and FPGA devices. The fast Fourier transform kernel is used in floating-point and fixed-point approaches which are compared and contrasted across the unique processing architectures.