Transistency Models: Memory Ordering at the Hardware-OS Interface
Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, Margaret Martonosi · IEEE Micro · 2017
This article introduces the transistency model, a set of memory ordering rules at the intersection of virtual-to-physical address translation and memory consistency models. Using their COATCheck tool, the authors show how to rigorously model, analyze, and verify the correctness of a given system's microarchitecture and software stack with respect to its transistency model specification.