Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect
Jiangyuan Gu, Shouyi Yin, Shaojun Wei · 2017
With the process scaling into nano-scale VLSI technology, the increasingly serious aging issues (e.g. NBTI aging effect) bring a significant threat to system reliability. Coarsegrained reconfigurable architectures (CGRAs) exhibit the feature to reconfigure different mapping schemes (Maps) dynamically during loops execution, which can mitigate the aging issues on CGRAs effectively. In this paper, we propose a stress-aware loops mapping algorithm by jointing intra-kernel and inter-kernel stress optimizations strategies in the early phase of CGRA-mapped designs. With the pipelining technique, a stress-aware force-directed method is introduced in the intra-kernel optimization, avoiding many operations to be mapped on some certain PEs and reducing the stresses accumulated on them. By leveraging the dynamic reconfiguration, a multi-map scheduling method is proposed in the inter-kernel stress optimization to find a set of ordered maps to reconfigure dynamically, which diversifies PE usages and compensates for the accumulated stresses on different PEs among them. Experimental results show our proposed approach enlarges the maximum stress reduction up to 78.9% and improves the MTTF by 340.3% on average while keeping the optimized performance.