Testing of an 8-bit Sigma Delta ADC Based on Code Width Technique Using 45nm Technology
Yogita Tembhre, Anil Kumar Sahu · 2016
A novel design is exhibited in the paper presented here for an analog-to-digital converter (ADC) built-in self test (BIST) scheme using code-width technique. An 8-bit sigma-delta ADC BIST scheme is introduced. The 8 bit sigma-delta ADC with arbitrary faults is simulated in the given BIST scheme designed in CMOS 45nm technology. Different parametric faults have been detected here such as Differential Non Linearity (DNL), monotonicity fault and missing code fault. This architecture of ADC BIST is achieved by Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology. The power dissipation of the BIST circuit is 18mW for the power supply of 1V.