Hot Row Identification of DRAM Memory in a Multicore System
Xi Tao, Qi Zeng, Jih-Kwon Peir · 2017
Access locality in single-core system is not easily observed in multicore system due to interleaved requests from different cores. Requests that come to DRAM-based main memory is mapped to a specific bank in DRAM and accessed through row buffer in the bank. DRAM row-buffer conflicts occur when a sequence of requests on different rows goes to the same memory bank, causing much higher memory access latency than requests to the same row or to different banks.