Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects
Nijwm Wary, Pradip Mandal · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2017
This paper presents a current-mode triline ternarylevel coded differential signaling scheme for high-speed data transmission across on-chip global interconnects. An energy efficient current-mode triline transceiver pair suitable for this signaling scheme has been proposed. Compared with a voltage mode receiver with resistive termination, the proposed active terminated current-mode receiver reduces the signal current by 7.8 times and the signaling power by 2.6 times. Two data transmission schemes are proposed for using this transceiver pair. In the first scheme, two data streams are directly transmitted over the three lines link, thereby having a wire efficiency of 67%. In the second scheme, five data streams at half rate are encoded and serialized to send over the three lines, thereby having a wire efficiency of 83%. A prototype design has been implemented in a UMC 0.18-μm technology for an interconnect of length 5 mm. The measured energy efficiency of the triline transceiver in a direct transmission scheme for the data rate of 7.4 Gb/s is 0.61 pJ/bit. With the encoding scheme, the energy efficiency is 1.24 pJ/bit for a total data transmission of 9.25 Gb/s.