An experimental investigation into multiprocessor systems – Pipeline processing and common memory approaches
Surendra Bhargava · OhioLink ETD Center (Ohio Library and Information Network) · 1983
h e irnplementa t i o n of p i p e l i n e processing schene where one canputer can send d a t a t o another computer v i a a dedicated p a r a l l e l communication channel.Steady s t a t e timing a n a l y s i s , t e s t i n g and experimental r e s u l t s , a r e a l s o discussed.In t h i s approach s t o r e d sampled d a t a is assurned t o be t h e input t o the system.Chapter 5 dwells on v a r i o u s schemes f o r p i p e l i n e processing sampled d a t a from binary d a t a switches, loop s t r u c t u r e , software implemented 'FIFO' memory b u f f e r schemeand t h e i r experimental r e s u l t s .Chapter 6 d e a l s with the design, implementation, and a discussion of experimental r e s u l t s , of a comnon memory configuration.In this scheme each computer can t a l k t o another computer v i a a comon memory which can be accessed through a comon bus.Appendices A, B, and C present t h e Assembly Language Listing of t h e test programs, p r o g r ~m s f o r p i p e l i n e processing, and comon memory configuration respectively.These appendices a r e widely r e f e r r e d t o while discussing t h e software.Appendix D p r e s e n t s a d e t a i l e d d e s c r i p t i o n of t h e Heathkit system used f o r t h i s p r o j e c t .I t a l s o c o n t a i n s a discussion of MC68~38 MPUt h e h e a r t of t h e Heathkit systemand of PIA6821the most i m p r t a n t device f o r implementing the i n v e s t i g a t i n g schemes.CliAlTEH 2 IlISTI\IHUT1.:DMIC1i0 C0MPUTF:Ii NE'lWOIlf