A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications
Christopher Babecki · OhioLink ETD Center (Ohio Library and Information Network) · 2015
CHRISTOPHER BABECKI Security is becoming an increasing concern in today's computer applications.Unfortunately, most encryption/decryption algorithms are computationally expensive and often do not map efficiently to general purpose processors (GPPs) or reconfigurable fabrics like Field Programmable Gate Arrays (FPGAs).Fixed-function accelerators offer significant improvement in energy-efficiency, but they do not allow more than one application to reuse hardware resources.This work presents a new reconfigurable hardware framework called Memory-Array centric Hardware Accelerator (MAHA) for accelerating a wide array of security applications.It incorporates a coarse-grained datapath, support for lookup functions, and flexible interconnect optimizations, which enable on-demand pipelining and parallel computations in multiple light-weight processing elements.Through simulations, this work compares the performance of MAHA to a commercial GPPs and FPGAs.Results for a set of six common security applications show comparable latency between MAHA and FPGA implementations with 2.5X improvement in energy-delay product and 4X improvement in iso-area throughput.x