A Parallel Stochastic Number Generator With Bit Permutation Networks
Vikash Sehwag, Neeli Rashmi Prasad, Indrajit Chakrabarti · IEEE Transactions on Circuits & Systems II Express Briefs · 2017
Stochastic computing (SC) is a promising paradigm to realize low-complexity digital circuits that are tolerant to soft errors. Stochastic circuits include a stochastic number generator (SNG) to generate a stochastic number that corresponds to a given binary number. Conventional SNGs, which employ linear feedback shift registers (LFSRs) to generate stochastic numbers in a serial manner would cost significantly in time. In this brief, a parallel SNG has been proposed, which can generate stochastic numbers in parallel by transforming the input binary number to a modified unary number and permuting it using a bit permutation network. Further, a method to share a single LFSR among multiple SNGs has been presented. Experimental results show that the proposed SNG can achieve improvement in SC correlation and energy-delay-product by 28.57% and 4.32×, respectively, when compared to the existing shared LFSR-based SNG. For applications, such as edge detector, multiplier, and complex multiplication, the proposed SNG has achieved reduction in execution time and area-delay-product by up to 1000× and 9×, respectively, as compared to others.