A 3-wire SPI Protocol Chip Design with Application-Specific Integrated Circuit (ASIC) and FPGA Verification
Min‐Chun Tuan, Shih‐Lun Chen, Yu‐Kuen Lai, Chun‐Chieh Chen, Ho-Yin Lee · Proceedings of the World Congress on Electrical Engineering and Computer Systems and Science · 2017
This paper presents a 3-wire SPI protocol chip design for application-specific integrated circuit (ASIC) and fieldprogrammable gate array (FPGA).It is the first study to realize SPI protocol by VLSI and FPGA technique for testing and verifying SPI protocol.The FPGA device is used as master device to control the ASIC design which is be as slave device.Moreover, the functions of SPI protocol is successfully worked by testing with oscilloscope.The ASIC design of this work contained 5.1 K gate counts and consumed 19 mW by using a TSMC 0.18 μm CMOS process.This work develops advanced VLSI architecture with only four pads (including system clock in ASIC design).