Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs
Nandeesha Veeranna, Benjamin Carrión Schäfer · 2016
Multi-Context Runtime Reconfigurable FPGAs have unique characteristics that make them extremely vulnerable to Hardware Trojan (HT). These FPGA families reconfigure themselves every clock cycle updating the functionality of the data path. A State Transition Controller (STC) typically holds the configuration code for each of the contexts. This architecture makes these type of architectures very efficient, but also extremely vulnerable to malicious alterations across any of the steps from design to fabrication of the FPGA. This work specifically targets the detection, but also the avoidance of HT being triggered in runtime reconfigurable FPGAs and in particular Coarse-Grained Runtime Reconfigurable Arrays (CGRRA). Experimental results show that our proposed method is very effective and has very little power overhead with no net area overhead.