Firm-core virtual FPGA for just-in-time FPGA compilation
Roman Lysecky, Kris Miller, Frank Vahid, Kees Vissers · Field Programmable Gate Arrays · 2005
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures, yielding software portability benefits. Researchers previously introduced the concept of a standard hardware binary to achieve similar portability benefits for hardware, using a JIT compiler to compile the hardware binary to an FPGA. The JIT compiler includes lean versions of technology mapping, placement, and routing algorithms that implement the standard hardware binary on a simple custom FPGA fabric designed specifically for JIT compilation. While developing a custom FPGA may be feasible for some applications, we propose implementing the simple FPGA fabric as a virtual FPGA. In this paper, we present a virtual FPGA, described using structural VHDL and thus representing a firm core that a designer can synthesize onto an existing FPGA. We synthesized the firm-core virtual FPGA onto Xilinx Spartan physical FPGAs and then mapped 18 benchmark circuits onto the virtual FPGA. Our results show a 6X decrease in performance and 100x more hardware resource usage, for the virtual FPGA approach compared to mapping the circuits directly to the physical FPGA fabric. While the hardware overhead is large, large commercial FPGA capacities may still mean that some applications can utilize a virtual FPGA approach if portability is more important than resource utilization. Furthermore, our work provides a baseline for future virtual FPGA approaches that may reduce the performance or area overhead through various means.