A 40nm CMOS high PSRR differential difference amplifier for sensor applications
Chean Hwa Chong · DR-NTU (Nanyang Technological University) · 2017
PSRR is becoming increasingly crucial as higher integration demands for noisy digital circuitry to packed closely to sensitive analog blocks. A high PSRR and low power amplifier is needed to drive a resistive 100 kΩ and capacitive 50 pF load over low frequencies as analog surrounding do not react at a high rate. This project has presented a three-stage differential difference amplifier (DDA) with PSRR of -92 dB near DC and -64 dB at 1 kHz. The DDA utilised supply independent biasing circuit for stable current output, a level shift flipped voltage follower (LSFVF) structured low-dropout (LDO) regulator to stabilise the supply voltage and a low pass filter (LPF) to attenuate all AC power supply ripple.