Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM
Chaobing Zhou, Libo Huang, Zhisheng Li, Tan Zhang, Qiang Dou · 2017
In embedded processors, the RAM resources required by branch predictor compared to desktop or server processors are far from being reached. Utilizing the limited resources to design superior performance branch predictor has become urgent challenge. In this paper, we exploit the performance of complex TAGE implemented in ultra-small RAM processor. We first define design space exploration problem of the TAGE under the constraints of given RAM size and maximum global history register length. Then, based on the trace-driven simulation, the improved Particle Swarm Optimization algorithm is used to efficiently explore the specific parameters, rewarding design parameters with high prediction accuracy under RAM ranging from 0.125KB to 4KB. We found that, for the traces of this paper, the parameters under the 1.5KB RAM explored by our algorithm can achieve adequate accuracy. The performance loss is considerably small if we reduce the RAM resources from 8KB to 1.5KB. In addition, the misprediction rate of 1.5KB TAGE are reduced by 63.41% compared to 1.5KB Bi-mode. And, 0.25KB TAGE has almost the same accuracy with 4KB GShare.