Test-set reordering for improving diagnosability
Cheng Qi Xue, Ronald DeShawn Blanton · 2017
Precise and accurate logic diagnosis for integrated circuits enables fast analysis of defect locations and their corresponding behaviors that leads to valuable feedback for achieving fast yield ramp-up. However during large-volume production, limited tester time or memory restrict the amount of data that can be recorded for each failing chip, thus making diagnosis more difficult. To help mitigate this challenge, a test-reordering method is developed to improve diagnosability for chips that fail scan-based logic testing. Experiment results show that the number of failing chips with perfect diagnostic resolution is increased by 10.6% and 5.1%, respectively, for two industrial designs after tests are reordered using the method described in this work.