Hybrid hard NoCs for efficient FPGA communication
Tianqi Liu, Naveen Kumar Dumpala, Russell Tessier · 2016
Recent research has shown that the integration of a custom-silicon network-on-chip (NoC) into an FPGA fabric can significantly help on-chip communication bandwidth. Although not appropriate for all communication, FPGA hard NoCs provide a scalable infrastructure that will increase in importance as FPGA sizes increase. To date, most FPGA hard NoC implementation has focused on packet-switched routing which requires dynamic run-time decision making to transfer data from source to destination. In this paper we explore expanding hard NoC routers to support both packet-switched and prescheduled time-multiplexed communication. By limiting the use of energy-hungry routing buffers, time-multiplexed routing allows for throughput-predictable data transport with reduced energy consumption versus packet-switching for a variety of traffic patterns. The area overhead required to convert a packet-switched router to a hybrid packet-switched/time-multiplexed version is minimal (about 9%). In this research, we show significant NoC energy improvement (about 33%) while maintaining or improving packet latency values versus packet switching for select data traffic patterns.