On the Reuse of VHDL Modules into SystemC Design
N.Agliada Nagliada, A.Fin Afin, Franco Fummi, Maurizio Martignano, G.Pravadelli Gpravadelli · 2001
More and more the SystemC description language is used to model and simulate new hardware designs. The need of integrating new designs with already existing modules may lead to the generation of heterogeneous models, specifications, based both on SystemC and on VHDL (or Verilog). In this scenario cosimulation is necessary to verify the heterogeneous system description. This paper presents a method to remove the above heterogeneity based on automatic translation of VHDL descriptions into SystemC. Of course, the presented approach is viable only if the automatic translation respects the original behaviour, specified in VHDL. This way, the adoption of a homogenous system model allows the efficient execution of simulations sessions aiming to assess the feasibility and convenience of reusing already existing modules.