Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing
Shaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan, Cécile Grèzes, Pedram Khalili-Amiri, Kang L. Wang, Puneet Gupta · 2017
In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected on die. These components are then used to realize FIR filter and AdaBoost (machine-learning algorithm). 3X–37X energy advantage is shown for the proposed SC compared with CMOS binary arithmetic ASIC and SC designs.