A high performance FPGA implementation of 256-bit Modular multiplication processor over GF(p)
Xiuze Dong, Xiaonan Zhang · 2016
FPGA implementation of Modular multiplication over GF(p) is not fast enough to apply to the request of high-performance applications. This work proposes an improved modular multiplication algorithm based on carry-save multiplication and generic reducer. The improved algorithm mainly utilizes serial-parallel hybrid structure. According to the proposed modular multiplication algorithm, the paper finishes a high performance modular multiplier processor on FPGA. Synthesis result on ALTERA Stratix EP3SL340F1760C2 shows that our modular multiplication processor can complete a 256-bit modular multiplier in 0.39 μs, and clock frequency is 60.32MHz. Compared with the previous modular multipliers, the paper spends lesser time, nearly decreasing 20%. Besides, the design does not occupy DSP block elements in hardware resources, which is not only beneficial to the actual hardware implementation, but also has the very good portability.