Emerging Technologies in On-Chip and Off-Chip Interconnection Network
Ashif Iqbal Sikder · OhioLink ETD Center (Ohio Library and Information Network) · 2016
The number of processing cores on a chip is increasing with the scaling down of transistors to meet the computation demand.This increase requires a scalable and an energy and latency efficient network to provide a reliable communication between the cores.Traditionally, metallic interconnection networks are used to connect the cores.However, according to the International Technology Roadmap for Semiconductor (ITRS), metallic interconnection networks would not be able to meet the future on-chip communication demands due to the energy and latency constraints.Thus, this thesis focuses on the novel on-chip network designs employing the emerging technologies, such as wireless and optics, to provide a scalable and an energy and latency efficient network.In this thesis, I propose an on-chip network architecture called Optical and Wireless Network-on-Chip (OWN) and extend OWN to construct Reconfigurable Optical and Wireless Network-on-Chip (R-OWN) architecture.OWN and R-OWN both leverage the advantages of optics and wireless technologies while circumventing the limitations of these technologies.The end result is that OWN and R-OWN both can provide a maximum of three hops communication between any two cores for a 256 to 1024 core networks.My simulation results with synthetic traffic demonstrate that, for 1024-core architectures, OWN requires 34% more area than hybrid-wireless architectures and 35% less area than hybrid-photonic architectures [1].In addition, OWN consumes 30% less energy per bit than hybrid-wireless architectures and 14% more energy per bit than hybrid-photonic architectures [1].Moreover, OWN shows 8% and 28% improvement in saturation throughput compared to hybrid-wireless and metallic architectures respectively [1].On the other hand, for 256-core architectures, R-OWN requires 3.9% and 12% less area compared to metallic and hybrid-wireless