Transformation of VHDL Descriptions into DEVS Models for Fault Modeling and Simulation
Laurent Capocchi, Fabrice Bernardi, Dominique Fédérici, Paul-Antoine Bisgambiglia · 2003
Abstract { We propose in this article an approach for the transformation of VHDL descriptions into DEVS models for an easy and fast fault simulation. VHDL al-lows description of the structure of a design, that is how it is decomposed into sub-designs, and how those designs are interconnected. The specication of the function of designs are performed using familiar programming lan-guage forms. One of the main problems is that today tools are unable to quickly and easily create and simu-late fault models directly from the VHDL descriptions. A way to solve this problem is to encapsulate these de-scriptions in easily simulable and evolutive models. We propose to use the DEVS formalism to achieve this en-capsulation.