A High Level Power modeling IP Methodology for SoC Design Based on FPGA Approach
David Elléouet, Nathalie Julien, Dominique Houzet · HAL (Le Centre pour la Communication Scientifique Directe) · 2005
Today and more tomorrow, Electronic system design requires to be concerned with the power consumption consideration. Currently, in a lot of design tools, the application power consumption budget is estimate after RTL synthesis. We propose in this article a methodology based on measurements allowing to model the application power consumption on FPGA with architectural and algorithmic parameters. So, The modeled applications can be added in a library in order to help the designer to determine quickly the best adequacy between high performances and low power consumption.