An Area Efficient FFT Structures Design by Sharing Arithmetic Units
Pradnya Pravin Zode, Dr.A.Y. Deshmukh · IOSR Journal of VLSI and Signal processing · 2017
Low power consumption has become apparent need in the area of VLSI digital signal processing. This gives rise to the need of minimization of silicon area which can be done by folding algorithm. As silicon area decreases power consumption of a circuit decreases. Folding transformation is a technique which reduces silicon chip area by combining various arithmetic operations into one operation by time scheduling technique.It is applied on iterative with appropriate folding set.This paper presents an approach to design fast Fourier transform (FFT) architectures using folding transformation.Proposed work is focused on design of efficient VLSI architecture for FFT using radix-3 algorithm which aims at reducing mainly area which results in reduction of power consumption and hardware complexity.A proper procedure for designing FFT architectures using folding transformation and register minimization techniques is projected.Results show that numbers of adders are reduced by 37.5 % and multipliers by 33.33% without changing characteristics of FFT algorithms.