IMPLEMENTATION OF LOW AREA AND DELAY BIT LEVEL ADDER-TREES
D. Jhansi, P. Eswara Rao · IJITR International Journal of Innovative Technology and Research - IJITR International Journal of Innovative Technology and Research · 2017
Digital filters are becoming ubiquitous in audio applications.As a result, good digital filter performance is important to audio system design.Digital filters uses finite precision to represent signals and are differ from analog filters as digital filters uses finite precision arithmetic to compute the filter response.In this project, FIR filter is implemented in Xilinx ISE using VERILOG language.VERILOG coding for the FIR filter is implemented in this project and waveforms are observed through simulation.Adder posses less weight when compared to multipliers in terms of silicon area and this is an advantageous in FIR structure.For this project the chosen multipliers are booth and Wallace and the considered adders are carry save and carry skip.In this project we have to develop an RTL for the structures and verify the functionality of the structures along with performing the synthesis using Xilinx synthesizer.The results are compared in terms of area (LUT'S), power, delay and memory for various fir structures.I.