A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs
Ehsan Ghasemi · TSpace (University of Toronto) · 2015
Due to rapidly expanding data size, there is increasing need for scalable, high-performance, and low-energy frameworks for large-scale data computation. In this thesis, we build a dataflow architecture that harnesses FPGA resources within a distributed analytics platform creating a heterogeneous data analytics framework. This approach leverages the scalability of existing distributed processing environments and provides easy access to custom hardware accelerators for large-scale data analysis. We prototype our framework within the Apache Spark analytics tool running on a CPU-FPGA heterogeneous cluster. As a specific application case study, we have chosen the MapReduce paradigm to implement a multi-purpose, scalable, and customizable RTL accelerator inside the FPGA, capable of incorporating custom High-Level Synthesis (HLS) MapReduce kernels. We demonstrate how a typical MapReduce application can be simply adapted to our distributed framework while retaining the scalability of the Spark platform.