Fault tolerance design for NoCs
Sa’ed Abed, Mohammad H. Alshayeji, Zahraa N. Abdullah, Zainab Al-Saeed · 2017
As the industry of Network of Chips (NoCs) evolves, the reliability and performance of these systems are becoming more critical requirement. The fault tolerance issue is an essential factor that has a direct impact on the reliability of the system. Many techniques were developed to boost the fault tolerance capability of NoCs. This is either implemented on the routing algorithm level or architecture level. This paper analyzes previous work that enhances the fault tolerance by modifying the router architecture. The model of Partial Virtual Sharing (PVS) architecture was modified to improve the fault tolerance capability. We proposed a technique to implement fault tolerance at the input unit of the router architecture. Additional enhancements to implement fault tolerance at the output unit of the router was proposed and implemented too. The reliability of the proposed design was evaluated and compared based on the Mean Time Between Failure (MTBF) metric. The proposed design had shown a remarkable improvement of 263.2% over existing approaches.