A technique of ASIC peak current estimation based on the resolution method
Tatiana V. Garbulina, S. V. Gavrilov, Andrey V. Korshunov, Daria I. Ryzhova, Волобуев Павел Сергеевич · 2017
As the technology decreases beyond the 28nm node, the area of VLSI elements and supply voltage level reduce significantly, and the level of integration increases. This leads to new effects such as crosstalk, voltage drop at power supply rails (IR-drop effect), the substrate noise and others. The peak current becomes one of the most important factors affecting the combinational CMOS circuits design flow. The maximum current value of CMOS IC is used to find IR-drop value and supply buses width. The existing methods of upper bound estimate do not provide the required accuracy for the peak current value estimation problem. The aim of this paper is to improve the accuracy and validity of the peak current upper bounds based on the resolution method. The proposed approach finds the maximal subset of gates that can switch at the same time thus providing the peak current. The hypergraph of logical restrictions is constructed with the help of the resolution method. The vertices of the hypergraph correspond to the outputs of the gates. Several vertices of the hypergraph can be connected by the only edge. The edge determines the simultaneous switching prohibition for the gates outputs belongs to this edge. A hypergraph is solved by the branch and bound method to find out the maximum IC current consumption. A comparison of branch and bound method with a standard worst-case IC peak current estimation method is made.