Design of low power decimal logarithmic converter
Riaz-ul-haque Mian, Md. Liakot Ali · 2017
The paper presents the design of an efficient low power decimal logarithmic converter. The technique is based on shift operation along with a precision unit which is used to prevent unnecessary scan of full memory table. Precision level is user programmable. It does not require multiplication or division circuitry which in turn makes it low power. The synthesized results show that the proposed technique costs (6002 logic element) and consuming power (only 47.37mW) which is lowest than other related algorithm. The design has been implemented in FPGA platform and proposed design outperforms all the existing design of the said topic.