Hardware-efficient folded SC polar decoder based on k-segment decomposition
Xiao Liang, Chuan Zhang, Shunqing Zhang, Xiaohu You · 2016
In this paper, a hardware-efficient folded SC polar decoder based on k-segment decomposition is first proposed. The proposed k-segment scheme employs (k - 1) N1/k-bit decoders to implement the original N-bit decoder, and reduces the number of mixed-nodes from (N - 1) to (k ă 1)( N1/k- 1) with slightly increased latency. In addition, pipelining technique, partial parallel processing, and pre-computation are employed to refine the timing issue resulting from folding scheme. Meanwhile, the hardware utilization ratio (HUR) of processing elements (PEs) is drastically increased. Both SC decoders with (N = 8,k = 3) and (N = 1024,k = 2) are implemented with Altera Stratix V FPGA. The former one requires only 13.46% ALMs and 10.66% register compared to the k = 1 scheme at the cost of slightly increased latency. The latter one consumes only 55.86% ALMs compared to the k = 1 scheme. Thus, the proposed k-segment decoder is suitable for scenarios requiring high-HUR.