RTL Don't Care Path Identification and Synthesis for Transforming Don't Care Paths into False Paths
Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara · 2007
Given a register-transfer level (RTL) circuit meeting a design specification, the RTL circuit may contain some functionally unused paths from one register to another within the design specification. Designers of the circuit may know some of the functionally unused paths during design processes, but not all of the functionally unused paths. If designer-unknown and functionally unused paths are identified systematically at RTL and its information about the paths are propagated to gate-level, the corresponding gatelevel paths can be eliminated from the target of testing. Otherwise, they must be the target of testing. We consider testing such paths to be futile. In this work, wefirst present a method of identifying the functionally unused paths using RTL information, and also address synthesis for transforming the identified paths into false paths. As a result, our approaches contribute to identification of many untestable paths and reduction of the futile testing.