A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation
Nidhi Batra, Shashwat Kaushik, Anil Kumar Gundu, Mohammad Hashmi, G. S. Visweswaran, Anuj Grover · 2016
With emerging deep submicron technology, device variations limit the SRAM performance and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell among other figure of merits (FOMs) governs the yield in SRAMs. Variations in the scaled SRAMs increase the probability of cells becoming weak. To ensure reliability of SRAMs it is important to identify such cells post fabrication. In this work, we propose a correlation based test methodology to detect the weak bits in SRAMs with respect to SNM. The proposed methodology efficiently measures effectiveness of test at CAD level. It enables designer to compare tests for their accuracy in identifying weak bits at nominal test conditions. We compare the traditional weak pull-up (PU) test with Word line (WL) boosting test technique for 64 Mb SRAM in 28nm FDSOI technology. We show that WL boost test method is more effective than the conventional weak PU test and that it is able to screen weak bits beyond 6σ. We also presented a WL boost circuit for detecting weak bits, which requires minimal design complexity.