Guiding Locality Optimizations for Graph Computations via Reuse Distance Analysis
Abdel‐Hameed A. Badawy, Donald Yeung · IEEE Computer Architecture Letters · 2017
This work addresses the problem of optimizing graph-based programs for multicore processors. We use three graph benchmarks and three input data sets to characterize the importance of properly partitioning graphs among cores at multiple levels of the cache hierarchy. We also exhaustively explore a large design space comprised of different parallelization schemes and graph partitionings via detailed simulation to show how much gain we can obtain over a baseline legacy scheme that partitions for the L1 cache only. Our results demonstrate the legacy approach is not the best choice, and that our proposed parallelization / locality techniques can perform better (by up to 20 percent). We then use a performance prediction model based on multicore reuse distance (RD) profiles to rank order the different parallelization / locality schemes in the design space. We compare the best configuration as predicted by our model against the actual best identified by our exhaustive simulations. For one benchmark and data input, we show our model can achieve 79.5 percent of the performance gain achieved by the actual best. Across all benchmarks and data inputs, our model achieves 48 percent of the maximum performance gain. Our work demonstrates a new use case for multicore RD profiles-i.e. as a tool for helping program developers and compilers to optimize graph-based programs.