Low latency network-on-chip router using static straight allocator
Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, Muhammad Nadzir Marsono · 2016
One clock cycle is the ideal latency for a network-on-chip (NoC) router to pass the received flit in the current cycle to its requested destination output port when there is no contention with other flits. In order to achieve this goal, a newly arrived flit is required to go through all router's pipeline stages to the switch traversal stage. In this paper, we present a low latency synchronized NoC router micro-architecture that achieves single clock cycle latency for packets traveling to the same direction using a static straight VC/SW allocator (SSA). In comparison to existing single clock cycle latency routers which require more complex VC/SW allocator or crossbar switch architectures, our proposed SSA has simpler architecture and works in parallel with the previously proposed baseline VC/SW allocator. The simulation results using six different synthetic traffic patterns shows SSA reduces the communication latency of a 2-cycle latency baseline router by 24% in average.