Real-Time Low-Power FPGA Architecture for Stereo Vision
Luca Puglia, Mario Vigliar, Giancarlo Raiconi · IEEE Transactions on Circuits & Systems II Express Briefs · 2017
Stereo vision is a well-known technique used to extract depth information from two or more images. In the last years, many efforts have been made to achieve high quality and efficient results. Although different techniques have been proposed to develop a working system. In this brief, we implemented a previous proposed algorithm for DNA sequence alignment, in order to align images on a field programmable gate array architecture. The design is embedded in a full processing pipeline for the use on low budget boards. The main goal of the project is to develop a real-time device with low power consumption. Such requirements should allow the use in critical and battery dependent applications. The written code is well parametrized and the synthesis is supported for different image resolution and disparity levels. Thanks to an easy refactoring, it is possible to migrate the architecture to every FPGA present on the market. The design reaches the processing ability of 1024×768 pixels, 64 disparity levels, 30 FPS with a power usage on chip of only 0.17 W.