FPGA based performance analysis of multiplier policies for FIR filter
Aneela Pathan, Tayab Din Memon, Sharmeen Keerio, Imtiaz Hussain Kalwar · 2016
In this work, comparative analysis of Booth and Wallace Tree multiplier architectures is presented using Altera small commercial FPGA devices. Comparison is done with respect to resources consumed and maximum frequency achieved for different multiplier bit width. The synthesis results show tradeoff that Booth multiplier offers better performance at the cost of more chip area. This is very useful to guide in choosing suitable VLSI architecture as per required application.