MODELING AND INTEGRATION OF CONNECTION BLOCK AND MULTI TECHNOLOGY LOGIC CLUSTER WITH ENHANCEMENT FOR THE SECOND GENERATION MT-FPGA
Prashanth Nt Pulipaka · OhioLink ETD Center (Ohio Library and Information Network) · 2006
In this technological era, real time applications mandate the design of complex circuits that involve multi-energy domain interaction.While past research has concentrated only on developing and optimizing application specific designs, the current research is looking into the design of generic multi-domain reconfigurable FPGAs with interaction between the digital, analog and mixed technology domains.Recent work at the University of Cincinnati has led to the development of a Multi-Technology Field Programmable Gate Array (MT-FPGA).Significant investigation in various design aspects has been carried out by doing the layout of the basic architecture.However, since SPICE simulators that perform the timing and functionality check are limited by the complexity of the circuit designed, it is difficult to evaluate the entire architecture unless the chip design is fabricated.This involves significantly more cost and time.Another option for evaluating chip architecture is to generate HDL models for the design and simulate using a HDL simulator.With this resource in place, the design could be thoroughly tested for any size of the architecture.The current thesis involves developing VHDL/VHDL-AMS structural models for two of the major components of the Second Generation MT-FPGA architecture, viz.Multi-Technology Logic Cluster (MTLC) and i Connection Block (CB).The delay associated with each of the primary components in the structural design is obtained by performing SPICE simulations on those individual components.The two blocks are then integrated and tested by targeting various applications on to the design.The timing results are compared with results obtained by testing a fabricated chip that contains the combination of these blocks.An enhancement has been made on the carry logic design in the MTLC that allows performing an N-bit arithmetic operation depending on the size of the entire architecture.To get a complete understanding of the functioning of the MT-FPGA, a 1x2 array structure has been developed by instantiating all the essential components of the MT-FPGA viz.MTLC, CB, Switch Block and IO Block.Applications that perform analog to analog communication, digital to digital communication and analog to digital communication were targeted onto this structure.