Logic optimization of AES S-Box
Shreenivas Pai N, S Raghuram, M Chennakrishna, A.S. Varun Karthik · 2016
This paper presents the implementation of Rijndael S-Box using combinational logic for the SubByte transformation in the Advanced Encryption Standard algorithm for ASIC. The main focus of this project is on achieving reduction in area occupancy and power consumption for the S-box module. We have realized an optimized implementation of the S-box in the Verilog HDL, and have subsequently synthesized it using 90nm CMOS standard cell library. Using a novel method of design reuse in the S-Box logic, the optimized design implemented, consumes 146 cells and the total power dissipation of 32,911 nW which is significantly lower when compared to the existing digital logic implementations.